In raster-type computer graphics display systems, a frame buffer memory is used to store pixel data. Typically, the frame buffer memory is arranged as an array, and the entry at a particular row and column in the array represents the intensity value of a corresponding pixel on the display device. (In the case of RGB display systems, each entry in the frame buffer includes intensity information corresponding to each of the R,G and B components of a pixel.) In operation, the pixel intensity values stored in the frame buffer memory are read in a repeating raster pattern and sent to a digital-to-analog converter module that drives the display device.
The display device also employs a repeating raster pattern to refresh the pixels that constitute the display. For example, in a CRT display device, horizontal and vertical deflectors are used to scan an electron beam in a left-to-right, top-to-bottom raster pattern that results in a brief periodic excitation for each pixel. After the beam has reached the right-most pixel in a given row of pixels, the beam quickly retraces to the left-most pixel in the next row. During this horizontal retrace movement, the intensity of the beam is reduced or "blanked" so that no pixels will be excited until the beam reaches its new starting position for the next row. (For purposes of this discussion, the phrase "horizontal scan interval" will be used to describe the period of time required for the beam to scan across all of the pixels in one row and then retrace to the beginning of the next row.) Likewise, after the beam has reached the last pixel of the last row, the beam quickly retraces to the left-most pixel in the top row so that the raster pattern may begin again. During this vertical retrace movement, the intensity of the beam is once again blanked to avoid affecting the displayed image.
By way of further background, it is an artifact of the evolution of display technology that a vertical retrace conventionally includes a wait time after the beam has snapped back to the top-left part of the display and before it resumes scanning across visible pixels. In older-technology display systems, this wait time was necessary in order for the analog circuits that move the beam to settle after the retrace. The length of this wait time is usually equal to the length of several horizontal scan intervals. For purposes of this discussion, the phrase "raster scan period" will be used to describe the period of time required for the beam to scan across all of the pixels in the entire display and then retrace to the beginning of the next row, including the just-described wait time.
While it is possible to change pixel data in the frame buffer memory at any time during a raster scan period, it is known that changing frame buffer data in the middle of a scan period may result in undesirable visual effects such as noise or tearing appearing in the image being displayed.
One method that has been used to solve this problem has been to write to the frame buffer memory only during the vertical retrace interval. While the latter technique does avoid the introduction of artifacts into the displayed image, it requires that all writes to the frame buffer must wait until vertical blank to be executed. Thus, when this technique is employed, the average wait time for all such writes will be one half of the length of one raster scan period. This wait time represents a compromise of speed in return for enhanced picture quality.
A second method that has been used to solve this problem in the past has been to use first and second frame buffer memories. This second technique of using first and second frame buffer memories is known as double buffering. In higher-end double-buffered systems, pixel data in the first frame buffer (the "viewable" or "front" buffer) is displayed while an image is rendered into the second frame buffer (the "non-viewable" or "back" frame buffer). Once the image has been completely rendered into the second frame buffer, the buffers are "swapped" so that the second frame buffer becomes the viewable buffer and the first frame buffer becomes the non-viewable frame buffer. A new frame is then rendered into the first buffer, and the buffers are swapped again. Such a solution provides the advantage that writes to the non-viewable frame buffer may occur at any time. However, the system must still wait until vertical blank occurs before the buffers are swapped. Moreover, such a system is more expensive to implement because of the cost of the redundant frame buffer memory and the overhead associated with swapping the two frame buffers.
In lower-end double-buffered systems, the buffers are never swapped; rather, one buffer is always viewable, and the other is always non-viewable. The pixel data in the non-viewable buffer is simply copied into the viewable buffer once a frame has been completely rendered. To make the transfer efficiently, use is generally made of a block transfer engine or "BLT engine." While such lower-end double-buffered systems are less expensive to implement than true buffer-swapping systems, they also suffer from the previously-describe drawback that BLT operations may only occur during vertical refresh if visual defects are to be avoided.
It is therefore an object of the present invention to reduce the average wait time required to perform frame buffer BLT operations in computer graphics display systems.
It is a further object of the present invention to perform such reduced-wait-time frame buffer BLT operations without introducing unwanted visual artifacts into the displayed image.